Method of processing variable size blocks of data by storing numbers representing size of data blocks in a fifo

ABSTRACT

A digital data processing system receives compressed variable length encoded digital data in the form of variable length codewords in contiguous variable speed Blocks of data. The boundary signals between adjacent codewords are determined and a demultiplexer sequentially sorts the serial digital data among a plurality of parallelly connected buffers for reducing the bit read speed of the buffers. A corresponding plurality of variable length decoders decodes the data from the buffers and outputs the data in parallel form to a multiplexer where it is reassembled into a serial expanded data stream. The incoming data includes selector information in fixed length headers that are separated, buffered and variable length decoded for controlling the demultiplexer. In one aspect of the invention, the data is sorted into substantially equal sized groups of integral codewords for equalizing the loading of the parallel buffers. In another aspect of the invention, the Block boundary marker signals are processed through much smaller auxiliary buffers using counters to keep track of the Block boundary marker signals for synchronization with the data flowing through the buffers.

DIVISIONAL REISSUE APPLICATIONS

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 5,563,920. The reissue applications are applicationSer. Nos. 12/000,338 (the present application) filed Dec. 11, 2007, and12/453,735 filed May 20, 2009, all of which are divisional reissues ofU.S. Pat. No. 5,563,920.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Pat. No. 5,285,276, entitled BI-RATEHIGH DEFINITION TELEVISION SIGNAL TRANSMISSION SYSTEM, issued Feb. 8,1994, in the name of R. Citta and discloses an invention claimed in,U.S. Pat. No. 5,424,733, entitled PARALLEL PATH VARIABLE LENGTH DECODINGFOR VIDEO SIGNALS, issued Jun. 13, 1995, in the names of the presentinventors, all of which are assigned to Zenith Electronics Corporation.

BACKGROUND OF THE INVENTION AND PRIOR ART

This invention relates in general to data processing systems and inparticular to a video data recovery and expansion system for use inconnection with a digital high definition television system. Therecently tested high definition television sysem of Zenith ElectronicsCorporation and AT&T Corporation includes a video compression scheme forcompressing 37 MHz information for transmission over a 6 MHz widetelevision channel.

U.S. Pat. No. 5,285,276, describes a temporally oriented videocompression system in which compressed video information is transmittedin the form of motion vectors and difference signals with the motionvectors identifying previous portions of a frame of video that closelymatch the current portion and the difference signals representing thedifferences between the previous and current portions. The videoinformation has a bandwidth of about 37 MHz and may comprise aprogressively scanned video signal in the form of successive frames ofbinary video data having a vertical periodicity equal to the NTSCstandard (i.e. about 59.4 Hz) and a horizontal periodicity equal tothree times the NTSC standard (i.e. about 47.25 KHz). The data is in theform of a series stream of binary pixel values that have been transformcoded in the frequency domain to develop discrete cosign transformcoefficients. The transform coding process provides a series of clustersof spectral transform coefficients for each frame of video, with eachcluster of coefficients corresponding to a different spatial region ofthe video image. Each cluster, for example, may comprise an 8×8 array ofcoefficients with 14,400 clusters representing an entire video frame.The coefficient clusters are serially applied to a perceptual modellingsystem which develops an output that reflects the perceptual nature ofthe corresponding portion of the video image. The video data is thencompressed in accordance with a selected compression algorithm. Onewell-known compression technique does not send all of the transformcoefficients, the coefficients whose omission will have the leastnoticeable effect on the received image being dropped. The remainingcoefficients are variable length encoded and sent as a series ofcodewords of unequal bit length, with the shortest codewords beingassigned to those values that are most probable.

As further discussed in U.S. Pat. No. 5,285,276, the data may be rankedby importance, i.e. control data may be sent in more robust initial datasegments, followed by data of the next level of importance such asmotion vectors, etc. It will be noted that the number of motion vectorsand difference signals may vary from frame to frame depending upon theperceptual nature of the video information in the frame and itsrelationship to the previous frame. The compressed variable lengthencoded information is assembled into Blocks consisting of a fixednumber of 8×8 coefficient arrays, from most of which some coefficientshave been omitted. Included with each Block is a Block header referredto as a selector, that consists of a fixed number of variable lengthencoded codewords containing the selector information. The selectorinformation identifies which coefficients have been omitted from the 8×8arrays in the Block and the total number of coefficients in the Block.The Blocks are assembled into data frames, each frame comprising apreselected number of equal length data segments. Each data segment hasan initial fixed length segment sync portion, a fixed length datasegment header and Block data, i.e. selector and coefficient data. Thedata segment header has a pointer that indicates the location in thedata segment where the first Block beginning, if any, in that datasegment occurs. Thus the selector data and coefficient data may berecovered by counting codewords and coefficients.

It will be noted that since the size of a Block is variable and the sizeof a data segment is fixed, the number of Blocks in a data segment willvary in accordance with the amount of compression. Therefore, severalBlocks may be contained in a single data segment, or a single Block ofdata may extend over several data segments. As to the variable lengthencoding of the Block data, any of a well known number of encodingsystems may be used such that the data or codewords may be joined, i.e.sequentially transmitted without breaks therebetween. The receivingsystem can produce a state table for determining the boundaries orjunctions between adjacent codewords. The encoding form known as Huffmanencoding is presently preferred. This is all by way of background to thepresent invention which will be understood not to be restricted to anyparticular form of encoding or processing.

The problem solved by the present invention is caused by the fact thatthe variable signal groups of compressed data supplied to the buffersmust be processed along with synchronizing or reset signals. Since thecompressed data buffers are of the fifo type, an equal size auxiliaryfifo buffer is required for the synchronizing signals to keep everythingin synchronism. This is a very expensive solution, however, and thepresent invention is directed to a system for significantly reducing thesize of the auxiliary buffer memory required for processing the syncsignals.

OBJECTS OF THE INVENTION

A principal object of the invention is to provide a novel digital dataprocessing system.

Another object of the invention is to provide a processing system forvariable sized groups of compressed data that minimizes memoryrequirements.

A further object of the invention is to provide an improved method ofmaintaining synchronism between variable sized groups of compressed dataand accompanying synchronizing signals.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects and advantages of the invention will be apparentupon reading the following description in conjunction with the drawings,in which:

FIG. 1 is a block diagram of a television transmission system utilizingthe invention; and

FIG. 2 is a block diagram illustrating operation of the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In FIG. 1, a transmitter 10 includes an encoder 12 for receiving videofrom a suitable source and processing it in any of a variety of ways,including the one specified in U.S. Pat. No. 5,285,276 by developingmotion vectors and discrete cosign transform coefficients for thedifference signals. The data is supplied to a variable length encoder 14in which the data is compressed and formatted in the form of codewordsof variable length. The output of variable length encoder 14 is at afixed video frame rate resulting in a variable data rate which, inaccordance with the preferred embodiment, averages about 17 megabits persecond. The variable rate data is applied to a compressed data (CD)buffer 16 which outputs data at a fixed data rate of 17 megabits persecond. The data is transmitted by any suitable means, e.g. over the airor by cable, to a receiver 11 which includes a compressed data buffer(CD) 18, a variable length decoder (VLD) 20, an uncompressed data buffer(UD) 22 and a selector 24. The uncompressed data buffer 22 is shown in adashed line block to simplify the operational description of theprocessing system.

The receiver requirements can best be understood by considering thatselector 24 must provide pixel data in parallel form (at an assumed 8bits per pixel), at a rate of about 75 megabytes per second. This 75megabytes per second rate is referred to as the pixel clock (pclock). Toachieve this rate, selector 24 requests data as needed (in parallelform) from VLD 20 via its request (req) line. The selector adds or fillsin 0's for omitted coefficients in the transmitted Blocks of data. Ittherefore doesn't request as much data from VLD 20 for a Block that hasomitted coefficients. The result is a relatively low data rate betweenVLD 20 and selector 24 when processing that Block. For Blocks of datawith no coefficients dropped, selector 24 must receive all coefficientsat the pclock rate. To supply selector 24 with data at the pclock rate,VLD 20 must request data from CD buffer 18 at the rate of one variablelength codeword per pclock. For example, assume a time period in whichall incoming variable length codewords are of maximum 8 bit length.Because VLD 20 receives data serially, the data rate is 8×pclock betweenCD buffer 18 and VLD 20. This is a very high rate (8×75 MHz) at which toread data out of conventional memory. Hence, the CD buffer 18 in thereceiver is placed before VLD 20 to keep the buffer size reasonable.(Buffering after VLD 20 would require a buffer of much larger size.)

A circuit modification that helps to reduce the buffer size includesanother buffer UD 22 in the dashed line box. Since worst case situations(no significant compression of data) will persist for relatively shortand infrequent time periods, UD 22 provides data to selector 24 at thepclock rate while reading data from VLD 20 at a somewhat lesser rate.The result is that the rate at which data is read from CD buffer 18 issomewhat reduced. However, UD buffer 22, which stores expanded data,would need to be very large to effect a significant reduction in thedata rate from CD buffer 18. The problem remains in that the high datarate between the CD buffer and the VLD requires the use of a veryexpensive high speed memory for the compressed data buffer.

The invention claimed in U.S. Pat. No. 5,424,733, above significantlyreduces the reading speed requirement for the compressed data buffer bysplitting the data among a number of buffers that operate in parallel.Referring to FIG. 2, compressed data and data segment sync signals areapplied to a first separator DS1. The data segment sync signals mark theboundaries between each of the fixed length data segments. DS1 separatesthe data segment header from the Block data in the data segments andsends the Block data to a compressed data output. DS1 determines thestarting points in the compressed data stream for some of the Blocks,i.e. the first Block beginning, if any, in a data segment from the datasegment header information. Specifically, a pointer in the data segmentheader points to the first Block beginning in the data segment. Thisinformation is used to create a partial Block boundary marker signal forsynchronization of the subsequent circuitry. The compressed data andpartial Block boundary marker signals are applied to a second dataseparator DS2.

DS2 includes means for finding the separation points between each of theindividual variables length codewords in the compressed data stream.Such means may conveniently take the form of separate variable lengthdecoders that are dedicated primarily to the task of finding thesecodeword boundaries. A partial Block boundary marker signal from DS1identifies a known, fixed number of following codewords as selector datafor the Block. A variable length decoder decodes the data counting thisknown, fixed number of codewords to identify the boundary in thecompressed data stream between the selector data and the coefficientdata. The compressed selector data is sent to the compressed selectordata output of DS2 and the subsequent coefficient data is sent to thecompressed data output of DS2. The portion of the decoded selector datathat identifies the number of coefficient codewords in the Block issaved and used to control the VLD which decodes the identified number ofcoefficient codewords before the next Block (and the new selector data)is encountered. DS2 stops routing the compressed data stream to thecompressed data output and switches back to the compressed selector dataoutput at that point. The remainder of the decoded selector data and allof the decoded coefficient data is discarded in DS2. DS2 also generatesa group boundary marker signal that denotes the boundaries betweengroups (i.e. an integral number of codewords) in the compressedcoefficient data stream at the compressed data output. The integralnumber is determined according to an algorithm to be discussed. In theevent of errors in the received data, the variable length decoders inDS2 will be quickly resynchronized by the partial Block boundary markersignal from DS1. The compressed data and group boundary marker signalsare applied to a demultiplexer and grouper 30 for demultiplexing andassembling the codewords into groups (determined by the algorithm)consisting of an integral number of codewords, the boundaries betweenthe groups being determined by the group boundary marker signal. Thecompressed selector data signal from DS2 is supplied, along with a dataclock signal, to a compressed data buffer 34.

The clock signal is supplied to the WR (write) terminal of a CD buffer34, while the data signal is applied to its I (input) terminal. Theoutput terminal O of buffer 34 supplies the compressed selector data toa selector data variable length decoder 39. VLD 39 controls the rate oftransmission of data from buffer 34 by means of a request line which iscoupled to the R (read) terminal of buffer 34. The partial Blockboundary marker signal supplied from DS1 to DS2 is present for only thefirst-occurring Block beginning in a data segment as described above.DS2 also develops a complete Block boundary marker signal thatidentifies each Block boundary when the separation points between theend of the compressed coefficient data and the beginning of thecompressed selector data, as described above, are determined. Anauxiliary buffer 35 is operated in parallel with buffer 34 formaintaining synchronism between the data (as it is processed) and thecomplete Block boundary marker signals. This arrangement for processingthe marker signals constitutes the subject of the present invention andresults in a significant reduction in the required size of the auxiliarybuffer.

An input bit counter 32 and an output bit counter 37 flank the auxiliarybuffer 35. The data clock signal is applied to input bit counter 32. Thecount value of input bit counter 32 is supplied to the data input of theauxiliary buffer 35. The reset terminal of input bit counter 32 and thewrite terminal of auxiliary buffer 35 are supplied with the completeBlock boundary marker signal from DS2. The output of auxiliary buffer 35is applied via a parallel load bus to output bit counter 37 which isstepped by the request signal from VLD 39. The count value of output bitcounter 37 is supplied to an “all zero” detector 38 which develops areset signal for VLD 39, for counter 37 and a lead signal for auxiliarybuffer 35. The selector data is applied to a selector/multiplexer 41 forcontrolling operation thereof. VLD 39 also generates a complete Blockboundary marker signal for selector/multiplexer 41. As indicated, thebuffers 34 and 35 are of the first-in, first-out (fifo) type that arewell known in the art.

Returning to DS2, demultiplexer and grouper 30 accepts the incomingserial data and the group boundary marker signal from DS2 and apportionsthe data into groups, each consisting of an integral number ofcodewords, among a plurality of parallelly connected compressed databuffers 50-57. The dashed line joining the buffers 50-57 indicates thatbuffers, corresponding to output terminals 1-6 of the demultiplexer andgrouper 30, are omitted. It will be understood that the output terminals0-7 are arbitrary in number and that each output terminal has the sameprocessing structure, i.e. buffers and variable length decoders,connected thereto. It will therefore suffice to describe operations forone output, it being understood that data at the other outputs isprocessed in an identical manner.

The data from terminal O is applied to the input terminal of CD buffer50. The data clock signal is applied to the WR terminal of CD buffer 50and to an input bit counter 40. An auxiliary buffer 60, an output bitcounter 70 and a zero detector 80 are connected in a manner similar tothe connection of auxiliary buffer 35, output bit counter 37 and zerodetector 38 described above. A variable length decoder 90 receives theserial data from CD buffer 50, decodes it, and applies the decoded datain a parallel format to an uncompressed data buffer 100. The output ofuncompressed buffer 100 is supplied to the selector and multiplexer 41,which also includes means for uncompressing the compressed data. It willbe noted that the VLD by its nature converts compressed data to a fixedlength output and broadly performs some expansion. In practice, thevariable length encoded codewords are decoded to a fixed 8 bit length.This is distinct from the uncompressing of the compressed data thatoccurs after the VLD.

A similar arrangement of elements coupled to output terminal 7 ofdemultiplexer and grouper 30, i.e. CD buffer 57, auxiliary buffer 67,bit counters 47 and 77, VLD 97 and uncompressed buffer 107 function inthe same way to develop a parallel output of a block of data, which isassembled into a single serial stream by selector/multiplexer 41.

The parallel buffer arrangement will now be discussed. As mentioned, theincoming data is formatted such that the boundaries between codewordscan be determined in the decoding process. Since the uncompressed datacan reach extremely high rates, the plurality of parallel buffers 50-57is employed to operate on sequential portions of the data stream. Sincethe required speed for each buffer is effectively divided by the numberof buffers, relatively low cost fifo memories may therefore be used forthe buffers. With the codewords being of variable length, the groupingof the codewords to load the parallel buffers substantially equally isvery important. The sizes or bit lengths of the codeword groups aredetermined with an algorithm based upon selecting a nominal group bitlength equal to the maximum codeword size and adding successivecodewords until the nominal size is reached or exceeded. When thisoccurs, the nominal bit length is subtracted from the actual number oftotalled bits and compared with another total developed from thedifference between the totalled number of bits minus the last-addedcodeword. The codeword arrangement that provides the smallest differenceis selected as the group and demultiplexer 30 supplies that group ofdata to buffer 50 and switches to its next output for the next group ofdata. The process proceeds in a cyclical manner with each of the outputsof demultiplexer and grouper 30 receiving a group of data for itsassociated buffer. With the arrangement, the loading of the buffers issubstantially equalized so that no one buffer is loaded significantlyfaster or more fully than any other buffer. This contributes greatly tosystem economy and enables the smaller size buffers to process theinformation. It will be appreciated that the number of buffers need notbe eight, but any number can be employed with equal effect. Thatinvention is the subject matter of the U.S. Pat. No. 5,424,733.

The subject matter of the present invention is the provision of theinput and output bit counters to enable the use of an auxiliary bufferof a significantly smaller size than the CD buffer while preservingsynchronism between the data that is being supplied to the CD buffer andthe complete Block boundary marker signal. Counter 40, for example,counts up the bits written into CD buffer 50 until it is reset by thecomplete Block boundary marker signal. This signal is a pulse in whichthe trailing edge acts as a reset signal. The count total of counter 40is transferred (as a parallel N bit word) to the auxiliary buffer 60when its WR input is activated by leading edge of the complete Blockboundary marker signal. Both CD buffer 50 and auxiliary buffer 60 are ofthe fifo variety, and as the data is serially transferred to buffer 50,the N bit word, representing the number of bits in the Block of data, isclocked along. The Block of data supplied to buffer 50 may comprise anumber of groups totalling many hundreds of bits in length whereas thecorresponding word in auxiliary buffer 60 is only a few (N) bits long.When VLD 90 requests data from buffer 50, the parallel data in auxiliarybuffer 60 is loaded into the output counter 70 and the counter begins tocount down in response to signals on the request line. When the countercounts down to all zeros, the zero detector 80 generates a reset signal,which is applied to VLD 90, counter 70 and auxiliary buffer 60. Thus thesynchronization of the compressed data and the Block boundary markersignal is maintained without requiring a duplicate size buffer forhandling the boundary signal.

N is readily determined by letting X equal the maximum number ofexpected coefficient bits in a Block. Since there are eight parallelpaths and the X bits are approximately equally distributed to each ofthe parallel paths (CD buffers), any given buffer will hold a maximum ofX/8 bits. Since the binary representation of N is log₂(X/₈), the inputand output bit counters must be N bits wide.

As mentioned previously, selector VLD 39 reads data out of CD buffer 34and provides decoded selector data to the selector/multiplexer 41. Inresponse to the reset signal from zero detector 38 which corresponds tothe Block boundary points, VLD 39 sends a new complete Block boundarymarker signal (corresponding to the original Block boundary markersignal) to the selector/multiplexer 41.

The parallel VLD's (90-97) read data out of their corresponding CDbuffers (50-57), decode the data and output it in parallel form to theircorresponding UD buffers (100-107). VLD's 90-97 also keep track ofcodeword groups generated according to the previously described groupingalgorithm and produce group boundary signals (bits) which are passed tothe UD buffers along with the decoded codewords. The codeword data andgroup boundary signals pass through the UD buffers and are available tothe selector/multiplexer 41.

The selector/multiplexer 41 outputs expanded coefficient data at thepclock rate. In response to the reset (complete Block boundary markersignal) from selector VLD 39, selector/multiplexer 41 reads the selectordata for the current Block of data from selector VLD 39. Thisinformation indicates which coefficients have been omitted from theBlock of data and the total number of coefficients in the Block. Thus,the number of coefficients to be read from the parallel coefficient UDbuffers is determined and the point at which selector data must be readfor the next Block of data from selector VLD 39 is ascertained. Theselector/multiplexer fills in O's for the omitted coefficients.

To maintain proper ordering of the data at the output of theselector/multiplexer, data must be read from the parallel UD buffers agroup of codewords at a time. This grouping is determined by thepreviously described group boundary marker signals.

What has been described is a novel data processing system for decodingvariable length encoded compressed data while maintainingsynchronization that minimizes the need for fifo memories. It isrecognized that numerous changes in the described embodiment of theinvention will be apparent to those skilled in the art without departingfrom its true spirit and scope. The invention is to be limited only asdefined in the claims.

1. A method of dynamically processing variably sized Blocks ofcompressed data in a signal processing apparatus, the method comprisingcontinuously: providing a bit stream of the compressed data, thecompressed data being processed by, writing said compressed data into afirst first-in first-out (fifo) memory; developing input numbersrepresenting the sizes of said Blocks of compressed data; storing saiddeveloped input numbers in a second fifo memory: ; and reading saidstored input numbers from said second fifo memory to identify saidBlocks of compressed data as said Blocks of compressed data are beingread from said first fifo memory.
 2. The method of claim 1, furthercomprising: the compressed data being further processed by, developing aBlock boundary signal indicating the junctions between said Blocks ofcompressed data; developing said input numbers by counting bits in saidBlocks of compressed data under control of said Block boundary signal;and controlling operation of said second fifo memory with said Blockboundary signal.
 3. The method of claim 2, further including thecompressed data being further processed by, stepping an input counter todevelop said input numbers and stepping an output counter that is loadedwith said input numbers as they are read from said second fifo memory.4. The method of claim 3, further comprising the compressed data beingfurther processed by, developing a reset signal when said output counterhas been stepped a number of counts equal to the input number loadedtherein; and controlling the read out of said second fifo memory and thereset of said output counter with said reset signal.
 5. A method ofdynamically synchronously processing contiguous unequal size Blocks ofcompressed data comprising continuously: serially writing saidcompressed data into a first first-in first-out (fifo) memory;developing counts of the numbers of bits in each of said Blocks; storingsaid counts in a second fifo memory: ; and sequentially reading saidcounts from said second fifo memory for identifying corresponding Blocksof data as said Blocks of data are being read from said first fifomemory.
 6. The method of claim 5 wherein a Block boundary signaldenoting the boundaries between said contiguous unequal size Blocks isdeveloped and further comprising: controlling an input counter with saidBlock boundary signal for counting the number of bits in each of saidBlocks of data; controlling an output counter loaded with the storedcounts from said second fifo memory and operated by bits being read fromsaid first fifo memory for developing a reset signal in synchronizationwith said Block boundary signal; and resetting said output counter andcontrolling the reading of data from said second fifo memory with saidreset signal.
 7. A receiver for processing a continuous stream ofdigital data in contiguous Blocks of sequential bits wherein the numberof bits of data in each Block is not uniform comprising: a first and asecond first-in first-out (fifo) memory; an input counter and an outputcounter; means for writing said digital data to said first fifo memory;means for controlling said input counter to develop a countrepresentative of the number of bits in a Block of data supplied to saidfirst fifo memory and for writing said count to said second fifo memory;detection means for reading said count from said second fifo memory andfor loading said count in said output counter; and means for controllingsaid output counter as said digital data is being read from said firstfifo memory; said detection means comprising means for determining whenthe number of bits read from said first fifo memory equals the countloaded in said output counter for developing a reset signal and meansfor resetting said output counter and controlling said second fifomemory with said reset signal.
 8. The receiver of claim 7 wherein saidoutput counter controlling means comprises a variable length decodercoupled to said first fifo memory, said variable length decoderincluding a request line for reading said digital data from said firstfifo memory and for operating said output counter and wherein saiddetection means comprises means for resetting said variable lengthdecoder with said reset signal.
 9. The receiver of claim 8 wherein saiddetermining means comprises an all zeroes detector and wherein saidoutput counter is decremented responsive to said request line.
 10. Amethod of dynamically processing variably sized blocks of compresseddata in a signal processing apparatus, the method comprisingcontinuously: receiving a video bitstream including compressed data; andprocessing the compressed data in the video bitstream by variable lengthdecoding, the processing being based on inpput numbers representingsizes of Blocks of the compressed data by, sequentially writing thecompressed data into a first first-in first-out (fifo) memory,sequentially developing the input numbers representing the sizes of theBlocks of the compressed data, sequentially storing the developed inputnumbers in a second fifo memory, and sequentially reading the storedinput numbers from the second fifo memory in order to identify theBlocks of compressed data being read out from the first fifo memory. 11.The method of claim 10, wherein the first fifo memory and the secondfifo memory are arranged in a buffer memory.
 12. The method of claim 11,wherein a plurality of the buffer memories are arranged in parallel. 13.The method of claim 10, wherein the Blocks include at least one of 8×8arrays, partial blocks, frames, and header data.
 14. The method of claim13, wherein the bitstream includes header data and wherein the inputnumbers are developed based on at least one of marker signals, boundarysignal, starting points, and sync signals in the header data.